Generation Report - 8B10B Encoder-Decoder MegaCore Function v9.0

Entity Nameenc8b10b_enc8b10b
Variation Nameenc8b10b
Variation HDLVHDL
Output DirectoryE:\work\homework\rate_matching

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
enc8b10b_tb.vA verilog module with the top-level demo testbench for the core.
enc8b10b_run_modelsim.tclA Tcl script to automate the process of running the provided demo testbench with the IP functional simulation model.
enc8b10b_constraints.tclTool command language (Tcl) script used to set constraints.
enc8b10b_enc8b10b.ocpAn OpenCore Plus file, needed for time limited or tethered hardware evaluation.
enc8b10b_enc8b10b.vVerilog HDL RTL for MegaCore variation
enc8b10b.vhdA MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
enc8b10b.bsfQuartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
enc8b10b.vhoVHDL IP functional simulation model
enc8b10b.qipContains Quartus II project information for your MegaCore function variation.
enc8b10b.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
clkINPUT1
reset_nINPUT1
idle_insINPUT1
kinINPUT1
enaINPUT1
datainINPUT8
kerrOUTPUT1
dataoutOUTPUT10
validOUTPUT1
rdinINPUT1
rdforceINPUT1
rdoutOUTPUT1
rdcascadeOUTPUT1