| File | Description |
|---|
| dec8b10b_tb.v | A verilog module with the top-level demo testbench for the core. |
| dec8b10b_run_modelsim.tcl | A Tcl script to automate the process of running the provided demo testbench with the IP functional simulation model. |
| dec8b10b_constraints.tcl | Tool command language (Tcl) script used to set constraints. |
| dec8b10b_dec8b10b.ocp | An OpenCore Plus file, needed for time limited or tethered hardware evaluation. |
| dec8b10b_dec8b10b.v | Verilog HDL RTL for MegaCore variation |
| dec8b10b.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| dec8b10b.bsf | Quartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. |
| dec8b10b.vho | VHDL IP functional simulation model |
| dec8b10b.qip | Contains Quartus II project information for your MegaCore function variation. |
| dec8b10b.html | The MegaCore function report file. |