Generation Report - Triple Speed Ethernet MegaCore Function v9.1 |
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Entity Name | altera_tse_pcs_pma_gige | Variation Name | tse_pcs_sbi | Variation HDL | VHDL | Output Directory | /home/huan/work/quartus/rate_matching/tse_pcs_sbi |
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File SummaryThe MegaWizard interface is creating the following files in the output directory: |
File | Description |
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tse_pcs_sbi.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. | tse_pcs_sbi.cmp | A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function. | tse_pcs_sbi.bsf | Quartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. | tse_pcs_sbi.vho | VHDL IP functional simulation model | tse_pcs_sbi.qip | Contains Quartus II project information for your MegaCore function variation. | tse_pcs_sbi.html | The MegaCore function report file. |
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MegaCore Function Variation File PortsName | Direction | Width |
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gmii_rx_d | OUTPUT | 8 | gmii_rx_dv | OUTPUT | 1 | gmii_rx_err | OUTPUT | 1 | gmii_tx_d | INPUT | 8 | gmii_tx_en | INPUT | 1 | gmii_tx_err | INPUT | 1 | tx_clk | OUTPUT | 1 | rx_clk | OUTPUT | 1 | reset_tx_clk | INPUT | 1 | reset_rx_clk | INPUT | 1 | address | INPUT | 5 | readdata | OUTPUT | 16 | read | INPUT | 1 | writedata | INPUT | 16 | write | INPUT | 1 | waitrequest | OUTPUT | 1 | clk | INPUT | 1 | reset | INPUT | 1 | txp | OUTPUT | 1 | rxp | INPUT | 1 | ref_clk | INPUT | 1 | led_an | OUTPUT | 1 | led_disp_err | OUTPUT | 1 | led_char_err | OUTPUT | 1 | led_link | OUTPUT | 1 | gxb_cal_blk_clk | INPUT | 1 |
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