Synplicity FPGA Reference Manual
Input and Result Files

Extension

File

Description

.adc

Analysis Design Constraint

Contains timing constraints to use for stand-alone timing analysis. Constraints in this file are used only for timing analysis and do not change the result files from synthesis. Constraints in the .adc file are applied in addition to .sdc constraints used during synthesis. Therefore,.adc constraints affect timing results only if there are no conflicts with .sdc constraints. See Conflict Resolution for Timing Exceptions for information on how the tool prioritizes constraints.

You can foward annotate .adc constraints to your vendor constraint file without rerunning synthesis. See Incremental Output Netlist of the User Guidefor details.

For details on how to create this file, see Using the Stand-alone Timing Analyst of the User Guide.

.ini

Configuration and Initialization

Governs the behavior of the synthesis tool. You normally do not need to edit this file; use the Schematic Options dialog box, instead, to customize behavior. See HDL Analyst Options Command.

On the Microsoft® Windows® operating system, the .ini file is in the WINDOWS (or WINNT) directory. On UNIX workstations, it is in the windows subdirectory of your home directory (~/.synplicity, where ~ is your home directory, which can be set with the environment variable $HOME).

.nrf

Netlist Restructure

In the Synplify Premier software, displays the netlist restructure file view along with the HDL Analyst RTL view to perform zippering and bit slicing. For more information, see Netlist Restructure File Command.

.opt

Xilinx Options file

An editable text file containing place-and-route option information to use when running Xilinx place-and-route. For more information, see Xilinx Options File Command.

.prj

Project

Contains all the information required to complete a design. It is in Tcl format, and contains references to source files, compilation, mapping, and optimization switches, specifications for target technology and other runtime options.

.sdc

Constraint

Contains the timing constraints (clock parameters, I/O delays, and timing exceptions) in Tcl format. You can either create this file manually or generate it by entering constraints in the SCOPE window. For more information about creating the .sdc file, see Constraint Files.

.sfp

Design Plan

In the Design Planner option of the Synplify Premier software, contains the design plan for an implementation in Tcl format. The .sfp file is created when you assign a design plan to the critical path(s) in your design with the Design Planner. For example:

• Region definitions: size and location. Some region definitions are determined by target device and the place-and-route tools.
• Region assignments: assignment of logical instances to regions
• Special assignments: assignment of logical instances to special chip resources like block RAMs or block Mults (Xilinx), or MACs (Altera DSPs)
• Pin assignments: assignment of I/Os to specific FPGA device pin numbers

.vhd

Source files (VHDL)

Design source files in VHDL format. See VHDL and VHDL Language Support for details. For information about using VHDL and Verilog files together in a design, see Using Mixed Language Source Files.

.v

Source files (Verilog)

Design source files in Verilog format. For more information about the Verilog language, and the synthesis commands and attributes you can include, see Verilog and Verilog Language Support. For information about using VHDL and Verilog files together in a design, see Using Mixed Language Source Files.