Synplicity FPGA Reference Manual
Input and Result Files

Extension

File

Description

.areasrr

Hierarchical Area Report

Reports area-specific information such as sequential and combinational ATOMS, RAMs, DSPs, and Black Boxes on each module in the design. See Hierarchical Area Report.

_cck.rpt

Constraint Checker Report

Checks the syntax and applicability of the timing constraints in the .sdc file for your project and generates a report (project_name_cck.rpt). See Constraint Checking Report for more information.

.est

Module area estimation file

In the Synplify Premier product, contains an area estimate for each design module. This information appears in the RTL and Technology views.

_est.srr

Area estimation log

In the Synplify Premier product, logs area estimate information. This is the file displayed by View -> View Estimation Log.

.info

Design component files

Design-dependent. Contains detailed information about design components like state machines or ROMs.

.fse

FSM information file

Design-dependent. Contains information about state machine encodings.

.pfl

Message Filter criteria

Output file created after filtering messages in the Messages window.

Results file:

• .edf
• .acf
• .vqm

Vendor-specific results file

Results file that contains the synthesized netlist, written out in a format appropriate to the technology and the place-and-route tool you are using. Generally, the format is EDIF, but there could be vendor-specific formats, like .acf or .vqm for Altera, or the Xilinx .edf format. Specify this file on the Implementation Results panel of the Options for Implementation dialog box (Implementation Results Panel).

.sap

Synplify Annotated Properties

This file is generated after the Annotated Properties for Analyst option is selected in the Device panel of the Options for Implementation dialog box. After the compile stage, the tool annotates the design with properties like clock pins. You can find objects based on these annotated properties using Tcl Find. For more information, see Tcl find CommandUsing the Tcl Find Command to Define Collections.

.sar

Archive file

Output of the Synplicity Archive utilility in which design project files are stored into a single archive file. Archive files use Synplicity Proprietary Format. See Archive Project Command for details on archiving, unarchiving and copying projects.

.srd

Intermediate mapping files

Used to save mapping information between synthesis runs. You do not need to use these files.

.srm

Mapping output files

Output file after mapping. It contains the actual technology-specific mapped design. This is the representation that appears graphically in a Technology view.

.srp

RTL design plan view

In the Synplify Premier product, a partitioned RTL-view file, containing regions and netlists. Double-clicking this file displays a design plan view of your design (same as HDL Analyst ->RTL->Floorplanned View).

.srr

Synthesis log file

Provides information on the synthesis run, as well as area and timing reports. See Log File, for more information.

.srs

Compiler output file

Output file after the compiler stage of the synthesis process. It contains an RTL-level representation of a design. This is the representation that appears graphically in an RTL view.

.ta

Customized Timing Report

In the Synplify Pro and Synplify Premier product, contains the custom timing information that you specify through Analysis->Timing Options. See Analysis Menu, for more information.

.tah

Connectivity-based timing report file

In the Synplify Premier product, a timing report output to the Implementation Results view in the Project view. This timing report, generated after the mapper phase, contains a hierarchical display of groups of connected critical paths called islands. See Basic Operations in the Schematic Views for more information.

_ta.srm

Customized mapping output file

In the Synplify Pro and Synplify Premier products, creates a customized output netlist when you generate a custom timing report with HDL Analyst->Timing Analyst. It contains the representation that appears graphically in a Technology view. See Analysis Menu for more information.

.tap

Timing Annotated Properties

This file is generated after the Annotated Properties for Analyst option is selected in the Device panel of the Options for Implementation dialog box. After the compile stage, the tool annotates the design with timing properties and the information can be analyzed in the RTL view and Design Planner. You can also find objects based on these annotated properties using Tcl Find. For more information, see Tcl find CommandUsing the Tcl Find Command to Define Collections

<vendor constraint file>

Constraints file for forward annotation

Contains synthesis constraints to be forward-annotated to the place-and-route tool. The constraint file type varies with the vendor and the technology. Refer to the vendor section for specific information about the constraints you can forward-annotate. Check the Implementation Results dialog (Implementation Options) for supported files. See Implementation Results Panel.

Verplex LEC

• .vfc
• .vlc
• .vm
• .vmc
• .vsc
• .vtc

Files for Verplex Conformal LEC

For the Synplify Pro software, usedUsed for input to the Verplex Conformal LEC tool. The .vtc file is the dofile, the .vm file is the synthesized netlist, and the other files contain constraints. For details about the files, see Xilinx MultiPoint Synthesis Flow, on page 10-67 of the User Guide.

.vif

Verification Interface Format

For certain Altera and Xilinx families, the VIF file uses Tcl commands to forward-annotate sequential optimizations performed during synthesis to any formal verification tool that can read Tcl files. These commands are only available with the Synplify Pro tool. For more information, see Tcl VIF Commands and Overview of the VIF Flow .

. vm

. vhm

Mapped Verilog or VHDL netlist

Optional post-synthesis netlist file in Verilog (.vm) or VHDL (.vhm) format. This is a structural netlist of the synthesized design, and differs from the original RTL used as input for synthesis. Specify these files on the Implementation Results dialog box (Implementation Options. See Implementation Results Panel.

Typically, you use this netlist for gate-level simulation, to verify your synthesis results. Some designers prefer to simulate before and after synthesis, and also after place-and-route. This approach helps them to isolate the stage of the design process where a problem occurred.

The Verilog and VHDL output files are for functional simulation only. When you input stimulus into a simulator for functional simulation, use a cycle time for the stimulus of 1000 time ticks.